The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a self-aligned contact (SAC).
In conventional semiconductor device fabrication processes, various attempts have been made to overcome limitations associated with mask overlay and patterning. A SAC method is one example of such attempts. According to the SAC method, an upper part of an electrode (e.g., gate electrode) is protected with a nitride layer using a selectivity ratio between nitride and oxide, and an oxide-based inter-layer insulation layer is etched to form a contact.
In consideration of SAC process conditions, if sufficient amounts of polymers are produced over a nitride layer formed over an upper part of an electrode patterned in a line type, a profile of the nitride layer usually becomes normal after SAC etching. However, the upper part of the electrode pattern is generally rounded. Thus, an amount of polymer deposited over the upper edge portions (hereinafter “shoulder portions”) of the electrode pattern is small, and nitride-based spacers formed on sidewalls of the electrode pattern physically conjoin with a hard mask of the electrode pattern. As a result, during SAC etching, the nitride layer formed over the upper part of the electrode pattern is damaged, resulting in a convex-concave profile.
FIGS. 1A to 1C are sectional views to illustrate a conventional SAC process. FIGS. 2A to 2C are transmission electron microscopic (TEM) images of semiconductor structures obtained by the conventional SAC process. Referring to FIG. 1A, a gate insulation layer 12 is formed over a substrate 11, and a plurality of gate patterns 13 are formed thereon. Each of gate patterns 13 includes a gate electrode 13A and a gate hard mask 13B, which are sequentially formed in a stack structure.
A passivation layer 14 is formed over the above resultant structure. Passivation layer 14 protects gate patterns 13. An inter-layer insulation layer 15 is formed over passivation layer 14, filling the space between gate patterns 13. Inter-layer insulation layer 15 is formed of an oxide-based material. A contact mask pattern 16 is formed over a portion of inter-layer insulation layer 15 where a SAC region is to be formed. Contact mask pattern 16 is usually formed of a nitride-based material, and has an opening wider than the space between gate patterns 13.
Referring to FIGS. 1B and 1C, the SAC designated region of inter-layer insulation layer 15 is etched using contact mask pattern 16 as an etch mask to form a SAC hole 17. Reference numeral 15A illustrated in FIG. 1B represents a first patterned inter-layer insulation layer. Reference numerals 12A, 14A, and 15B, illustrated in FIG. 1C, respectively represent a patterned gate insulation layer, a patterned passivation layer, and a second patterned inter-layer insulation layer during the formation of SAC hole 17. Since shoulder portions of gate patterns 13 are rounded, polymers are less likely to be deposited over the shoulder portions during etching of inter-layer insulation layer 15 (i.e., SAC etching), and thus, gate hard masks 13B are more likely to be damaged. This damage is illustrated in FIG. 1C and labeled as “P.” If gate hard masks 13B are severely damaged, a short failure may occur between each of gate electrodes 13A and a conductive material to fill SAC hole 17. Reference numerals 13C and 13X represents damaged gate hard masks and gate patterns during the SAC etching, respectively.
FIG. 2A illustrates a TEM image of a semiconductor structure obtained after sequential process steps illustrated in FIG. 1A. Gate patterns 13 have rounded upper parts. FIGS. 2B and 2C illustrate TEM images of semiconductor structures obtained after sequential process steps illustrated in FIGS. 1B and 1C, respectively.
Although SAC etching can be performed under the condition that produces lots of polymers to reduce damage to a gate hard mask, an inter-layer insulation layer between gate patterns may not be removed to a sufficient level. Accordingly, contact regions may not be opened properly.